As semiconductor devices become more highly integrated, conductive patterns in the semiconductor devices and therebetween have generally been reduced to minute sizes. Thus, due to high specific resistance of polysilicon that is commonly used as a wiring material for semiconductor devices, problems such as RC time delay and IR voltage reduction may occur.
In particular, in forming a cell gate of a flash memory device using polysilicon, performance of the flash memory device may be increased by reducing resistance of a word line, which may be achieved by forming a silicide layer on a polysilicon layer that serves as a control gate. However, in a flash memory device having a vertical stack type gate structure that includes a tunnel oxide film, a floating gate, a dielectric film, and a control gate, a length of the gate may be reduced according to a reduced design rule to be 50 nm or less. Thus, it may be even more difficult to form a silicide layer having a thickness sufficient to obtain a required gate resistance.
In order to obtain electrical characteristics desired for a gate electrode of the flash memory device, a control gate having a predetermined thickness may be required. In a gate structure, in order to increase a coupling ratio, which generally is an indicator of the coupling between a floating gate and the control gate when a voltage is applied to the control gate in a program operation, it may be necessary to increase a height of the gate structure according to the reduced design rule, and a gap between gate structures may also be reduced according to the design rule. As a result, an aspect ratio of the gap between the gate structures may increase.
When a metal silicide layer is formed on a plurality of gate structures formed with gaps having a large aspect ratio as described above, various unwanted problems can occur. For example, voids may be formed in an insulating layer between two adjacent gate structures or an undesired metal silicide layer may be formed on a surface of an active region of a semiconductor substrate.